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general description the DS1374 is a 32-bit binary counter designed to con- tinuously count time in seconds. an additional counter generates a periodic alarm or serves as a watchdog timer. if disabled, this counter can be used as 3 bytes of nonvolatile (nv) ram. separate output pins are pro- vided for an interrupt and a square wave at one of four selectable frequencies. a precision temperature-com- pensated reference and comparator circuit monitor the status of v cc to detect power failures, provide a reset output, and automatically switch to the backup supply when necessary. additionally, the reset pin is monitored as a pushbutton input for externally generating a reset. the device is programmed serially through a 2-wire bidirectional bus. applications portable instruments point-of-sale equipment medical equipment telecommunications features ? 32-bit binary counter ? second binary counter provides time-of-day alarm, watchdog timer, or nv ram ? separate square-wave and interrupt output pins ? 2-wire serial interface ? automatic power-fail detect and switch circuitry ? single-pin pushbutton reset input/open-drain reset output ? low-voltage operation ? trickle-charge capability ? -40? to +85? operating temperature range ? 10-pin ?op DS1374 2-wire, 32-bit binary counter watchdog rtc with t rickle charger and reset input/output ______________________________________________ maxim integrated products 1 1 2 3 4 5 10 9 8 7 6 v cc sqw int scl rst v backup x2 x1 top view sda gnd DS1374 sop pin configuration ordering information DS1374 x1 x2 crystal v cc v cc sqw scl sda int rst int rst gnd v backup v cc v cc n.o. pushbutton reset primary battery, rechargeable battery, or super capacitor cpu rpu rpu = t r /c b rpu t ypical operating circuit rev 0; 8/03 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin- package top mark DS1374u-18 -40? to +85? 10 ?op DS1374-18 DS1374u-3 -40? to +85? 10 ?op DS1374-3 DS1374u-33 -40? to +85? 10 ?op DS1374-33
DS1374 2-wire, 32-bit binary counter watchdog rtc with t rickle charger and reset input/output 2 _____________________________________________________________________ absolute maximum ratings recommended dc operating conditions (v cc = v cc min to v cc max , t a = -40? to +85?, unless otherwise noted.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage on v cc pin relative to ground.................-0.3v to +6.0v voltage on sda, scl, and wds relative to ground ....................................-0.3v to v cc + 0.3v operating temperature range ...........................-40 c to +85 c storage temperature range .............................-55 c to +125 c soldering temperature range .......see ipc/jedec j-std-020a parameter symbol conditions min typ max units DS1374-33 2.97 3.3 5.50 DS1374-3 2.7 3.0 3.3 supply voltage (notes 2, 3) v cc DS1374-18 1.71 1.8 1.89 v input logic 1 v ih (note 2) 0.7 v cc v cc + 0.3 v input logic 0 v il (note 2) -0.3 +0.3 v cc v DS1374-33 2.70 2.88 2.97 DS1374-3 2.45 2.6 2.7 power-fail voltage (note 2) v pf DS1374-18 1.51 1.6 1.71 v DS1374-33 1.3 3.0 v cc max DS1374-3 1.3 3.0 3.7 backup supply voltage (notes 2, 3, 4) v backup DS1374-18 1.3 3.0 3.7 v
DS1374 2-wire, 32-bit binary counter watchdog rtc with t rickle charger and reset input/output _____________________________________________________________________ 3 dc electrical characteristics (v cc = v cc min to v cc max , t a = -40? to +85?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units r1 (note 5) 250 r2 (note 6) 2000 trickle-charge current-limiting resistors r3 (note 7) 4000 ? input leakage i li (note 8) -1 +1 i/o leakage i lo (note 9) -1 +1 rst pin i/o leakage i lorst (note 10) -200 +1 ? sda logic 0 output (v ol = 0.4v) i olsda 3.0 ma v cc > 2v; v ol = 0.4v 3.0 1.71v < v cc < 2v; v ol = 0.2 v cc 3.0 ma rst , sqw, and int logic 0 outputs (note 11) i ol1 1.3v < v cc < 1.71v; v ol = 0.2 v cc 250 ? DS1374-18 75 150 DS1374-3 110 200 active supply current (notes 11, 12) i cca DS1374-33 180 300 ? DS1374-18 60 100 DS1374-3 80 125 standby current (notes 11, 13) i ccs DS1374-33 115 175 ? v backup leakage current (v backup = 3.7v) i backuplkg 100 na dc electrical characteristics ( v cc = 0v, v backup = 3.7v , t a = -40? to +85?, unless otherwise noted.) (note 1) parameter symbol conditions max typ max units v backup oscillator current (osc on); sqw off i bkosc1 (note 14) 400 700 na v backup oscillator current (osc on); sqw on (32khz) i bkosc2 (notes 14, 15) 600 1000 na v backup data-retention current (osc off) i backupdr 25 100 na
DS1374 2-wire, 32-bit binary counter watchdog rtc with t rickle charger and reset input/output 4 _____________________________________________________________________ ac electrical characteristics (v cc = v cc min to v cc max , t a = -40? to +85?, unless otherwise noted.) (note 1) (figure 1) parameter symbol conditions min typ max units fast mode 100 400 scl clock frequency (note 16) f scl standard mode 0 100 khz fast mode 1.3 bus free time between stop and start conditions t buf standard mode 4.7 ? fast mode 0.6 hold time (repeated) start condition (note 17) t hd:sta standard mode 4.0 ? fast mode 1.3 low period of scl clock t low standard mode 4.7 ? fast mode 0.6 high period of scl clock t high standard mode 4.0 ? fast mode 0 0.9 data hold time (notes 17, 18) t hd:dat standard mode 0 0.9 ? fast mode 100 data setup time (note 11) t su:dat standard mode 250 ns fast mode 0.6 start setup time t su:sta standard mode 4.7 ? fast mode 300 rise time of both sda and scl signals (note 19) t r standard mode 20 + 0.1c b 1000 ns fast mode 300 fall time of both sda and scl signals (note 19) t f standard mode 20 + 0.1c b 300 ns fast mode 0.6 setup time for stop condition t su:sto standard mode 4.7 ? c ap aci ti ve load for e ach bus li ne c b 400 pf pulse width of spikes that must be suppressed by the input filter t sp fast mode 30 ns pushbutton debounce pb db (figure 2) 250 ms reset active time t rst (figure 2) 250 ms oscillator stop flag (osf) delay t osf (note 20) 100 ms
DS1374 2-wire, 32-bit binary counter watchdog rtc with t rickle charger and reset input/output _____________________________________________________________________ 5 power-up/power-down characteristics (t a = -40? to +85?) (figure 3) parameter symbol conditions min typ max units v cc detect to recognize inputs (v cc rising) t rpu 250 ms v cc fall time; v pf(max) to v pf(min) t f 300 ? v cc rise time; v pf(min) to v pf(max) t r 0s warning: under no circumstances are negative undershoots, of any amplitude, allowed when the device is in write protection. note 1: limits at -40? are guaranteed by design and not production tested. note 2: all voltages are referenced to ground. note 3: v backup should not exceed v cc max or 3.7v, whichever is greater. note 4: the use of the 250 ? trickle-charge resistor is not allowed at v cc > 3.63v and should not be enabled. note 5: measured at v cc = typ, v backup = 0v, register 09h = a5h. note 6: measured at v cc = typ, v backup = 0v, register 09h = a6h. note 7: measured at v cc = typ, v backup = 0v, register 09h = a7h. note 8: scl only. note 9: sda and sqw and int . note 10: the rst pin has an internal 50k ? pullup resistor to v cc . note 11: trickle charger disabled. note 12: i cca ?cl clocking at max frequency = 400khz. note 13: specified with 2-wire bus inactive. note 14: measured with a 32.768khz crystal attached to the x1 and x2 pins. note 15: wdstr = 1. bbsqw = 1 is required for operation when v cc is below the power-fail trip point (or absent). note 16: c b ?otal capacitance of one bus line in pf. note 17: a device must internally provide a hold time of at least 300ns for the sda signal (referred to as the v ihmin of the scl sig- nal) to bridge the undefined region of the falling edge of scl. note 18: the maximum t hd:dat only has to be met if the device does not stretch the low period (t low ) of the scl signal. note 19: a fast-mode device can be used in a standard-mode system, but the requirement t su:dat to 250ns must be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max + t su:dat = 1000 + 250 = 1250ns before the scl line is released. note 20: the parameter t osf is the period of time the oscillator must be stopped for the osf flag to be set over the voltage range of 0v v cc v cc max and 1.3v v backup 3.7v. note 21: after this period, the first clock pulse is generated. note 22: this delay applies only if the oscillator is enabled and running. if the eosc bit is 1, the startup time of the oscillator is added to this delay.
DS1374 2-wire, 32-bit binary counter watchdog rtc with t rickle charger and reset input/output 6 _____________________________________________________________________ outputs v cc v pf(max) inputs high-z rst don't care v alid recognized recognized v alid v pf(min) t rst t rpu t r t f v pf v pf figure 3. power-up/power-down timing t rst pb db rst figure 2. pushbutton reset timing sda scl t hd:sta t low t high t r t f t buf t hd:dat t su:dat repeated start t su:sta t hd:sta t su:sto t sp stop start figure 1. data transfer on 2-wire serial bus
DS1374 2-wire, 32-bit binary counter watchdog rtc with t rickle charger and reset input/output _____________________________________________________________________ 7 i bat0sc1 vs. v bat square-wave off DS1374 toc01 v bat (v) supply current (na) 5.3 4.8 4.3 3.8 3.3 2.8 2.3 1.8 350 400 450 500 550 300 1.3 v cc = 0v i bat0sc2 vs. v bat square-wave on DS1374 toc02 400 450 500 550 600 650 700 750 800 350 v cc = 0v v bat (v) supply current (na) 5.3 4.8 4.3 3.8 3.3 2.8 2.3 1.8 1.3 i batosc1 vs. temperature v bat = 3.0v DS1374 toc03 temperature ( c) supply current (na) 80 60 40 20 0 -20 400 425 450 475 375 -40 v cc = 0v i cca vs. v cc (square-wave on) DS1374 toc04 v cc (v) supply current ( a) 5.3 4.8 3.8 4.3 2.8 3.3 2.3 75 100 125 150 175 200 225 250 275 50 1.8 oscillator frequency vs. v backup DS1374 toc05 v backup (v) frequency (hz) 5.3 4.8 4.3 3.8 3.3 2.8 2.3 1.8 32768.3 32768.4 32768.5 32768.6 32768.7 32768.8 32768.2 32768.1 32768.0 1.3 v cc = 0v v cc falling vs. rst delay DS1374 toc06 v cc falling (v/ms) reset delay ( s) 10 1 0.10 1 10 100 1000 0.1 0.01 100 v cc = 3.0v to 0v t ypical operating characteristics (v cc = +3.3v, t a = +25?, unless otherwise noted.)
DS1374 detailed description the DS1374 is a real-time clock with a 2-wire serial interface. it provides elapsed seconds from a user- defined starting point in a 32-bit counter (figure 4). a 24-bit counter can be configured as either a watchdog counter or an alarm counter. an on-chip oscillator cir- cuit uses a customer-supplied 32.768khz crystal to keep time. a power-control circuit switches operation from v cc to v backup and back when power on v cc is cycled. if a rechargeable backup supply is used, a trickle charger can be enabled to charge the backup supply while v cc is on. 2-wire, 32-bit binary counter watchdog rtc with t rickle charger and reset input/output 8 _____________________________________________________________________ pin description pin name function 1, 2 x1, x2 connections for a standard 32.768khz quartz crystal. the internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (c l ) of 6pf. pin x1 is the input to the oscillator and can optionally be connected to an external 32.768khz oscillator. the output of the internal oscillator, pin x2, is floated if an external oscillator is connected to pin x1. 3v backup connection for a secondary power supply. supply voltage must be held between 1.3v and 3.7v (-18 and -3) or 1.3v and 5.5v (-33) for proper operation. this pin can be connected to a primary cell such as a lithium button cell. additionally, this pin can be connected to a rechargeable cell or a super cap when used with the trickle-charge feature. 4 rst active-low, open-drain output with a debounced pushbutton input. this pin can be activated by a pushbutton reset request, a watchdog alarm condition, or a power-fail event. it has an internal 50k ? pullup resistor. 5 gnd ground 6 sda serial data input/output. sda is the input/output for the 2-wire serial interface. the sda pin is open drain and requires an external pullup resistor. 7 scl serial clock input. scl is the clock input for the 2-wire serial interface and is used to synchronize data movement on the serial interface. 8 int interupt. this pin is used to output the alarm interrupt or the watchdog reset signal. it is active-low open drain and requires an external pullup resistor. 9 sqw square-wave output. this pin is used to output the programmable square-wave signal. it is open drain and requires an external pullup resistor. 10 v cc dc power for primary power supply clock divider 32-bit counter mux 4.096khz 1hz x1 x2 8.192khz 32.768khz 1hz/0.96khz alarm/ wa tchdog stat/ctrl/ trickle 24-bit counter int control rst control 2-wire interface power control and trickle charge v cc v backup gnd sda scl rst sqw int figure 4. functional diagram
oscillator circuit the DS1374 uses an external 32.768khz crystal. the oscillator circuit does not require any external resistors or capacitors to operate. table 1 specifies several crys- tal parameters for the external crystal. figure 5 shows a functional schematic of the oscillator circuit. the startup time is usually less than 1 second when using a crystal with the specified characteristics. clock accuracy clock accuracy is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. additional error is added by crystal frequency drift caused by temperature shifts. external circuit noise coupled into the oscillator cir- cuit can result in the clock running fast. figure 6 shows a typical pc board layout for isolating the crystal and oscil- lator from noise. refer to application note 58: crystal considerations with dallas real-time clocks for detailed information. address map table 2 shows the address map for the DS1374 regis- ters. during a multibyte access, the address pointer wraps around to location 00h when it reaches the end of the register space (08h). on a 2-wire start, stop, or address pointer incrementing to location 00h, the current time is transferred to a second set of registers. these secondary registers read the time information, while the clock continues to run. this eliminates the need to reread the registers in case of an update of the main registers during a read. time-of-day counter the time-of-day counter is a 32-bit up counter. the contents can be read or written by accessing the address range 00h?3h. when the counter is read, the current time of day is latched into a register, which is output on the serial data line while the counter contin- ues to increment. w atchdog/alarm counter the contents of the watchdog/alarm counter, which is a separate 24-bit down counter, are accessed in the address range 04h?6h. when this counter is written, the counter and a seed register are loaded with the desired value. when the counter is to be reloaded, it uses the value in the seed register. when the counter is read, the current counter value is latched into a regis- ter, which is output on the serial data line while the counter continues to decrement. if the counter is not needed, it can be disabled and used as a 24-bit cache of nv ram by setting the wace bit in the control register to logic 0. if all 24 bits of the watchdog/alarm counter are written to zero when wace = 1, the counter is disabled and the af bit is not set. DS1374 2-wire, 32-bit binary counter watchdog rtc with t rickle charger and reset input/output _____________________________________________________________________ 9 countdown chain rtc x1 x2 c l 1 c l 2 crystal rtc registers figure 5. oscillator circuit showing internal bias network crystal x1 x2 gnd local ground plane (layer 2) guard ring figure 6. layout example parameter symbol min typ max units nominal frequency f o 32.768 khz series resistance esr 45 k ? load capacitance c l 6pf table 1. crystal specifications* * the crystal, traces, and crystal input pins should be isolated from rf generating signals. refer to application note 58: crystal considerations for dallas real-time clocks for addi- tional specifications .
DS1374 when the wd/ alm bit in the control register is set to a logic 0, the wd/ alm counter decrements every second until it reaches zero. at this point, the af bit in the sta- tus register is set and the counter is reloaded and restarted. if af is set when the watchdog function is enabled, the output selected by wdstr immediately becomes active. when the wd/ alm bit is set to logic 1, the wd/ alm counter decrements every 1/4096 of a second (approx- imately every 244?) until it reaches zero, sets the af bit in the status register, and stops. if wdstr = 0, the rst pin pulses low for 250ms, and accesses to the DS1374 are inhibited. at the end of the 250ms pulse, the af bit is cleared to zero, the rst pin becomes high impedance, and read/write access to the DS1374 is enabled. if aie = 1 and wdstr = 1, the int pin pulses low for 250ms. the pulse cannot be truncated by writ- ing either af or aie to zero during the low time of the int pin. if the wd/ alm counter is written during the 250ms pulse, the counter starts decrementing upon the pulse completion. at the completion, the af bit clears to zero and the int pin becomes high impedance. the wd/ alm counter can be reloaded and restarted before the counter reaches zero by reading or writing any of the wd/ alm counter registers. power-up/power-down reset and pushbutton reset functions a precision temperature-compensated reference and comparator circuit monitors the status of v cc . when an out-of-tolerance condition occurs, an internal power-fail signal is generated that forces the rst pin low and blocks read/write access to the DS1374. when v cc returns to an in-tolerance condition, the rst pin is held low for 250ms to allow the power supply to stabilize. if the eosc bit is set to a logic 1 (to disable the oscillator in battery-backup mode), the reset signal is kept active for 250ms plus the startup time of the oscillator. the DS1374 provides for a pushbutton switch to be connected to the rst output pin. when the DS1374 is not in a reset cycle, it continuously monitors the rst signal for a low-going edge. if an edge is detected, the DS1374 debounces the switch by pulling the rst pin low and inhibits read/write access. after the internal 250ms timer has expired, the device continues to moni- tor the rst line. if the line is still low, the DS1374 con- tinues to monitor the line, looking for a rising edge. upon detecting release, the DS1374 forces the rst pin low and holds it low for an additional 250ms. special purpose registers the DS1374 has two additional registers (07h?8h) that control the wd/ alm counter and the square-wave, interrupt, and reset outputs. 2-wire, 32-bit binary counter watchdog rtc with t rickle charger and reset input/output 10 ____________________________________________________________________ address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 function 00h tod counter byte 0 time-of-day counter 01h tod counter byte 1 time-of-day counter 02h tod counter byte 2 time-of-day counter 03h tod counter byte 3 time-of-day counter 04h wd/ alm counter byte 0 watchdog/alarm counter 05h wd/ alm counter byte 1 watchdog/alarm counter 06h wd/ alm counter byte 2 watchdog/alarm counter 07h eosc wace wd/ alm bbsqw wdstr rs2 rs1 aie control 08h osf 0 0 0 0 0 0 af status 09h tcs3 tcs2 tcs1 tcs0 ds1 ds0 rout1 rout0 trickle charger table 2. address map note: unless otherwise specified, the state of the registers is not defined when power is first applied.
control register (07h) bit 7/enable oscillator (eosc). when set to logic 0, the oscillator is started. when set to logic 1, the oscilla- tor is stopped. when this bit is set to logic 1, the oscilla- tor is stopped and the DS1374 is placed into a low-power standby mode (i ddr ). this bit is clear (logic 0) when power is first applied. when the DS1374 is powered by v cc , the oscillator is always on regardless of the state of the eosc bit. bit 6/wd/ a a l l m m counter enable (wace). when set to logic 1, the wd/ alm counter is enabled. when set to logic 0, the wd/ alm counter is disabled, and the 24 bits can be used as nv ram. this bit is clear (logic 0) when power is first applied. bit 5/wd/ a a l l m m counter select (wd/ a a l l m m ). when set to logic 0, the counter decrements every second until it reaches zero and is then reloaded and restarted. when set to logic 1, the wd/ alm counter decrements every 1/4096 of a second (approximately every 244?) until it reaches zero, sets the af bit in the status register, and stops. if any of the wd/ alm counter registers are accessed before the counter reaches zero, the counter is reloaded and restarted. this bit is clear (logic 0) when power is first applied. bit 4/battery-backed square-wave enable (bbsqw). this bit, when set to logic 1, enables the square-wave output when v cc is absent and when the DS1374 is being powered by the v backup pin. when bbsqw is logic 0, the sqw pin goes high impedance when v cc falls below the power-fail trip point. this bit is disabled (logic 0) when power is first applied. bit 3/watchdog reset steering bit (wdstr). this bit selects which output pin the watchdog-reset signal occurs on. when the wdstr bit is set to logic 0, a 250ms pulse occurs on the rst pin if wd/ alm = 1 and the wd/ alm counter reaches zero. the 250ms reset pulse occurs on the int pin when the wdstr bit is set to logic 1. this bit is logic 0 when power is first applied. bits 2, 1/rate select (rs2 and rs1). these bits con- trol the frequency of the square-wave output when the square wave has been enabled. table 3 shows the square-wave frequencies that can be selected with the rs bits. these bits are both set (logic 1) when power is first applied. bit 0/alarm interrupt enable (aie). when set to logic 1, this bit permits the alarm flag (af) bit in the status register to assert int (when intcn = 1). when set to logic 0 or intcn is set to logic 0, the af bit does not initiate the int signal. if the wd/ alm bit is set to logic 1 and the af flag is set, writing aie to zero does not trun- cate the 250ms pulse on the int pin. the aie bit is at logic 0 when power is first applied. DS1374 2-wire, 32-bit binary counter watchdog rtc with t rickle charger and reset input/output ____________________________________________________________________ 11 rs2 rs1 square-wave output frequency 00 1hz 01 4.096khz 10 8.192khz 11 32.768khz table 3. square-wave output frequency tcs3 tcs2 tcs1 tcs0 ds1 ds0 rout1 rout0 function xx xx 00 xx disabled xx xx 11 xx disabled xx x xxx00 disabled 10 1 001 01 no diode, 250 ? resistor 10 1 010 01 one diode, 250 ? resistor 10 1 001 10 no diode, 2k ? resistor 10 1 010 10 one diode, 2k ? resistor 10 1 001 11 no diode, 4k ? resistor 10 1 010 11 one diode, 4k ? resistor 00 0 000 00 power-on reset value table 4. trickle charge register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 eosc wace wd/ alm bbsqw wdstr rs2 rs1 aie
DS1374 status register (08h) bit 7/oscillator stop flag (osf). a logic 1 in this bit indicates that the oscillator either is stopped or was stopped for some period of time and can be used to judge the validity of the timekeeping data. this bit is set to logic 1 any time the oscillator stops. the following are examples of conditions that can cause the osf bit to be set: 1) the first time power is applied. 2) the voltage present on v cc is insufficient to support oscillation. 3) the eosc bit is turned off. 4) external influences on the crystal (i.e., noise, leak- age, etc.). this bit remains at logic 1 until written to logic 0. bit 0/alarm flag (af). a logic 1 in the alarm flag bit indicates that the wd/ alm counter reached zero. if wd/ alm is set to zero and the aie bit = 1, the int pin goes low and stays low until af is cleared. af is cleared when written to logic 0. this bit can only be written to logic 0. attempting to write logic 1 leaves the value unchanged. if wd/ alm is set to 1 and the aie bit = 1, the int pin pulses low for 250ms when the wd/ alm counter reaches zero and sets af = 1. at the pulse completion, the DS1374 clears the af bit to zero. if the 250ms pulse is active, writing af to zero does not truncate the pulse. trickle-charge register (10h) the simplified schematic in figure 7 shows the basic components of the trickle charger. the trickle-charge select (tcs) bits (bits 4?) control the selection of the trickle charger. to prevent accidental enabling, only a pattern of 1010 enables the trickle charger. all other patterns disable the trickle charger. the trickle charger is disabled when power is first applied. the diode select (ds) bits (bits 2, 3) select whether or not a diode is connected between v cc and v backup . if ds is 01, no diode is selected; if ds is 10, a diode is selected. the rout bits (bits 0, 1) select the value of the resistor connected between v cc and v backup . table 4 shows the resistor selected by the resistor select (rout) bits and the diode selected by the diode select (ds) bits. warning: the rout value of 250 ? must not be select- ed whenever v cc is greater than 3.63v. the user determines diode and resistor selection according to the maximum current desired for battery or super cap charging. the maximum charging current can be calculated as illustrated in the following example. assume that a system power supply of 3.3v is applied to v cc and a super cap is connected to v backup . also assume the trickle charger has been enabled with a diode and resistor r2 between v cc and v backup . the maximum current i max would therefore be calculated as follows: i max = (3.3v - diode drop) / r2 (3.3v - 0.7v) / 2k ? 1.3ma 2-wire, 32-bit binary counter watchdog rtc with t rickle charger and reset input/output 12 ____________________________________________________________________ bit 7 tcs3 1 of 16 select note: only 1010b enables charger 1 of 2 select v cc v backup r1 250 ? tcs 0-3 = trickle charger select ds 0-1 = diode select tout 0-1 = resistor select r2 2k ? r3 4k ? 1 of 3 select bit 6 tcs2 bit 5 tcs1 bit 4 tcs0 bit 3 ds1 bit 2 ds0 bit 1 rout1 bit 0 rout0 figure 7. programmable trickle charger bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 osf 0 0 0000af
as the super cap changes, the voltage drop between v cc and v backup decreases and therefore the charge current decreases. 2-wire serial data bus the DS1374 supports a bidirectional 2-wire bus and data transmission protocol. a device that sends data onto the bus is defined as a transmitter and a device receiving data is a receiver. the device that controls the message is called a master. the devices that are controlled by the master are slaves. a master device that generates the serial clock (scl), controls the bus access, and generates the start and stop condi- tions must control the bus. the DS1374 operates as a slave on the 2-wire bus. connections to the bus are made through the open-drain i/o lines sda and scl. a standard mode (100khz max clock rate) and a fast mode (400khz max clock rate) are defined within the bus specifications. the DS1374 works in both modes. the following bus protocol has been defined (figure 8): data transfer can be initiated only when the bus is not busy. during data transfer, the data line must remain sta- ble whenever the clock line is high. changes in the data line while the clock line is high can be interpret- ed as control signals. accordingly, the following bus conditions have been defined: bus not busy: both data and clock lines remain high. start data transfer: a change in the state of the data line from high to low, while the clock line is high, defines a start condition. stop data transfer: a change in the state of the data line from low to high, while the clock line is high, defines a stop condition. data valid: the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condi- tion and terminated with a stop condition. the number of data bytes transferred between the start and the stop conditions is not limited, and is determined by the master device. the informa- tion is transferred byte-wise and each receiver acknowledges with a ninth bit. a standard mode (100khz clock rate) and a fast mode (400khz clock rate) are defined within the 2-wire bus specifica- tions. acknowledge: each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse that is associat- ed with this acknowledge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge-related clock pulse. setup and hold times must be considered. a master must signal an end of data to the slave by DS1374 2-wire, 32-bit binary counter watchdog rtc with t rickle charger and reset input/output ____________________________________________________________________ 13 stop condition or repeated start condition repeated if more bytes are transfered ack start condition ack acknowledgement signal from receiver acknowledgement signal from receiver slave address msb scl sda r/w direction bit 12 678 9 12 89 3? figure 8. 2-wire data transfer overview
DS1374 2-wire, 32-bit binary counter watchdog rtc with tickle charger and reset input/output 14 ____________________________________________________________________ not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition. figures 9 and 10 detail how data transfer is accom- plished on the 2-wire bus. depending on the state of the r/ w bit, two types of data transfer are possible: data transfer from a master transmitter to a slave receiver. the first byte transmitted by the master is the slave address. next follows a number of data bytes. the slave returns an acknowledge bit after each received byte. data transfer from a slave transmitter to a mas- ter receiver. the master transmits the first byte (the slave address). the slave then returns an acknowl- edge bit. next follows a number of data bytes transmitted by the slave to the master. the master returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a ?ot acknowledge?is returned. the master device generates the serial clock puls- es and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condi- tion is also the beginning of the next serial transfer, the bus is not released. the DS1374 can operate in the following two modes: slave receiver mode (write mode): serial data and clock data are received through sda and scl. after each byte is received, an acknowledge bit is transmitted. start and stop conditions are rec- ognized as the beginning and end of a serial trans- fer. address recognition is performed by hardware after reception of the slave address and direction bit. the slave address byte is the first byte received after the master generates a start condition. the slave address byte contains the 7-bit DS1374 address, which is 1101000, followed by the direc- tion bit (r/ w ), which is zero for a write. after receiv- ing and decoding the slave address byte, the DS1374 outputs an acknowledge on sda. after the DS1374 acknowledges the slave address + write bit, the master transmits a word address to the DS1374. this sets the register pointer on the DS1374, with the DS1374 acknowledging the trans- fer. the master can then transmit zero or more bytes of data, with the DS1374 acknowledging each byte received. the register pointer increments after each data byte is transferred. the master gen- erates a stop condition to terminate the data write. slave transmitter mode (read mode): the first byte is received and handled as in the slave receiv- er mode. however, in this mode, the direction bit indicates that the transfer direction is reversed. serial data is transmitted on sda by the DS1374, while the serial clock is input on scl. start and stop conditions are recognized as the beginning and end of a serial transfer. address recognition is performed by hardware after reception of the slave address and direction bit. the slave address byte is the first byte received after the start condition is generated by the master. the slave address byte contains the 7-bit DS1374 address, which is 1101000, followed by the direction bit (r/ w ), which is 1 for a read. after receiving and decoding the slave address byte, the DS1374 outputs an acknowledge on sda. the DS1374 then begins to transmit data starting with the register address pointed to by the register pointer. if the register pointer is not written to before the initiation of a read mode, the first address that is read is the last one stored in the register pointer. the DS1374 must receive a not acknowledge to end a read. s 1101000 0 a xxxxxxxx a xxxxxxxx a xxxxxxxx a xxxxxxxx p data transferred (x+1 bytes + acknowledge) slave address s - start a - acknowledge p - stop r/w - read/write or direction bit data (n) register address data (n + 1) data (n + x) r/w figure 9. 2-wire write protocol s 1101000 1 a xxxxxxxx a xxxxxxxx a xxxxxxxx a xxxxxxxx /a data transferred (x+1 bytes + acknowledge) slave address s - start a - acknowledge p - stop /a - not acknowledge r/w - read/write or direction bit data (n) data (n + 1) data (n + x) data (n + 2) r/w figure 10. 2-wire read protocol
DS1374 2-wire, 32-bit binary counter watchdog rtc with tickle charger and reset input/output maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 15 2003 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .) chip information transistor count: 11,036 process: cmos substrate connected to ground thermal information theta-ja: 221?/w theta-jc: 39?/w

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